Analytical Eye-Diagram Determination for the Efficient and Accurate Signal Integrity Verification of Single Interconnect Lines
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Dongchul | - |
dc.contributor.author | Kim, Hyewon | - |
dc.contributor.author | Eo, Yungseon | - |
dc.date.accessioned | 2021-06-23T06:26:52Z | - |
dc.date.available | 2021-06-23T06:26:52Z | - |
dc.date.issued | 2012-10 | - |
dc.identifier.issn | 0278-0070 | - |
dc.identifier.issn | 1937-4151 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/31825 | - |
dc.description.abstract | In this paper, a new efficient and accurate analytical eye-diagram determination technique for interconnect lines is presented. The simplest input test signal model for the intersymbol interference analysis of high-speed data links is mathematically formulated. Since input test patterns for eye boundaries are determined analytically, it is considered very convenient and efficient. The proposed technique shows excellent agreement with the SPICE-based simulation in both eye height and jitter, i.e., within 5% error for nondiscontinuous data paths and 10% error for discontinuous data paths. The method is much more computation-time-efficient than the pseudorandom bit sequence-based SPICE simulation in the order of magnitude. | - |
dc.format.extent | 10 | - |
dc.language | 영어 | - |
dc.language.iso | ENG | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Analytical Eye-Diagram Determination for the Efficient and Accurate Signal Integrity Verification of Single Interconnect Lines | - |
dc.type | Article | - |
dc.publisher.location | 미국 | - |
dc.identifier.doi | 10.1109/TCAD.2012.2196277 | - |
dc.identifier.scopusid | 2-s2.0-84866608292 | - |
dc.identifier.wosid | 000308969600006 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.31, no.10, pp 1536 - 1545 | - |
dc.citation.title | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | - |
dc.citation.volume | 31 | - |
dc.citation.number | 10 | - |
dc.citation.startPage | 1536 | - |
dc.citation.endPage | 1545 | - |
dc.type.docType | Article | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | sci | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Interdisciplinary Applications | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | TRANSMISSION-LINES | - |
dc.subject.keywordPlus | DESIGN | - |
dc.subject.keywordPlus | SIMULATION | - |
dc.subject.keywordPlus | JITTER | - |
dc.subject.keywordAuthor | Eye diagram | - |
dc.subject.keywordAuthor | intersymbol interference (ISI) | - |
dc.subject.keywordAuthor | jitter | - |
dc.subject.keywordAuthor | signal integrity | - |
dc.subject.keywordAuthor | transmission line | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/6303934 | - |
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