Gate Engineering in TiN/La/TiN and TiLaN Metal Layers on Atomic-Layer-Deposited HfO2/Si
DC Field | Value | Language |
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dc.contributor.author | Kim, Hyo Kyeom | - |
dc.contributor.author | Lee, Sang Young | - |
dc.contributor.author | Yu, Il-Hyuk | - |
dc.contributor.author | Park, Tae Joo | - |
dc.contributor.author | Choi, Rino | - |
dc.contributor.author | Hwang, Cheol Seong | - |
dc.date.accessioned | 2021-06-23T06:55:56Z | - |
dc.date.available | 2021-06-23T06:55:56Z | - |
dc.date.created | 2021-01-21 | - |
dc.date.issued | 2012-07 | - |
dc.identifier.issn | 0741-3106 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/32270 | - |
dc.description.abstract | This letter compares TiN/La/TiN (TLT) and TiLaN (TLN) metal gates on HfO2/Si substrates, focusing on the flatband voltage (V-FB) modulation and interfacial layer (IL) scaling. The maximum V-FB modulation value of the TLT/HfO2/Si stack was -423 mV compared to the V-FB of the TiN single-metal case, which is superior to that of TLN (-247 mV). This is because the TiN barrier layer in the TLT metal stack prevents interfacial oxidation. Both TLT and TLN gate metals effectively shrink the IL thickness to values below 0.5 nm. In the case where the TLT metal gate was annealed at 600 degrees C for 30 s, the IL thickness was almost zero, and the equivalent oxide thickness was decreased to 0.8 nm even though the maximum temperature was limited to 600 degrees C. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | Institute of Electrical and Electronics Engineers | - |
dc.title | Gate Engineering in TiN/La/TiN and TiLaN Metal Layers on Atomic-Layer-Deposited HfO2/Si | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Park, Tae Joo | - |
dc.identifier.doi | 10.1109/LED.2012.2197369 | - |
dc.identifier.scopusid | 2-s2.0-84862881905 | - |
dc.identifier.wosid | 000305835300013 | - |
dc.identifier.bibliographicCitation | IEEE Electron Device Letters, v.33, no.7, pp.955 - 957 | - |
dc.relation.isPartOf | IEEE Electron Device Letters | - |
dc.citation.title | IEEE Electron Device Letters | - |
dc.citation.volume | 33 | - |
dc.citation.number | 7 | - |
dc.citation.startPage | 955 | - |
dc.citation.endPage | 957 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | STABILITY | - |
dc.subject.keywordPlus | TIN | - |
dc.subject.keywordAuthor | Lanthanum metal gate | - |
dc.subject.keywordAuthor | scavenging effect | - |
dc.subject.keywordAuthor | work function modulation | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/6213486 | - |
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