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고속 VLSI 회로에서 전송선의 지연시간 모델
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 어영선 | - |
| dc.date.accessioned | 2021-06-23T07:58:36Z | - |
| dc.date.available | 2021-06-23T07:58:36Z | - |
| dc.date.issued | 1999-11-01 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/33478 | - |
| dc.description.abstract | The transmission line effects of IC interconnects have a substantial effect on a high- speed VLSI circuit performance. The effective transmission line parameters are changed with the increase of the operation frequency because of the skin effect, proximity effect, and silicon substrate. A new signal delay estimation methodology based on the RLC-distributed circuit model is presented [2]. The methodology is demonstrated by using SPICE simulation and a high-frequency experiment technique. | - |
| dc.title | 고속 VLSI 회로에서 전송선의 지연시간 모델 | - |
| dc.type | Conference | - |
| dc.citation.conferenceName | 전자공학회 추계 학술대회 | - |
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Related Researcher
- EO, YUNG SEON
- ERICA 공학대학 (SCHOOL OF ELECTRICAL ENGINEERING)