Physics-Based Compact Model for III-V Digital Logic FETs Including Gate Tunneling Leakage and Parasitic Capacitance
- Authors
- Oh, Saeroonter; Wong, H. -S. Philip
- Issue Date
- Apr-2011
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Compact model; digital logic; gate tunneling leakage; parasitic capacitance; III-V compound semiconductor; III-V field-effect transistor (FET)
- Citation
- IEEE TRANSACTIONS ON ELECTRON DEVICES, v.58, no.4, pp.1068 - 1075
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON ELECTRON DEVICES
- Volume
- 58
- Number
- 4
- Start Page
- 1068
- End Page
- 1075
- URI
- https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/38174
- DOI
- 10.1109/TED.2011.2105875
- ISSN
- 0018-9383
- Abstract
- A physics-based compact model is developed for III-V field-effect transistors for digital logic applications. Quasi-ballistic ratios, trapezoidal quantum-well subband energy levels, and 2-D source/drain influence on both electrostatics and capacitance are considered. Furthermore, gate tunneling leakage current and parasitic capacitance models are included. These latter effects are important in future technology logic applications, particularly in circuits such as high-density cache arrays. In this paper, we describe the III-V compact model including the gate leakage current and parasitic capacitance analytical models. The efficacy of the compact model in a practical circuit environment is demonstrated using transient simulations of a 6T-static random access memory cell. In addition, we provide design guidelines for optimization of the intrinsic and the extrinsic structure with regard to the parasitic effects.
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