Strain Effectiveness of Gate-all-around Silicon Transistors with Various Surface Orientations and Cross-sections
- Authors
- Kim, Kihwan; Oh, Saeroonter
- Issue Date
- Feb-2019
- Publisher
- 대한전자공학회
- Keywords
- Gate-all-around; nanosheet; strain-effectiveness; sub-7 nm CMOS
- Citation
- JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.19, no.1, pp.24 - 29
- Indexed
- SCIE
SCOPUS
KCI
- Journal Title
- JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
- Volume
- 19
- Number
- 1
- Start Page
- 24
- End Page
- 29
- URI
- https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/3943
- DOI
- 10.5573/JSTS.2019.19.1.024
- ISSN
- 1598-1657
- Abstract
- We investigate the effect of strain on the device characteristics of gate-all-around (GAA) NMOS with various configurations, including crystal orientation, cross-sectional shape, and strain conditions, via device simulation. After verifying the strain dependence of mobility of various surface orientations with the literature, we apply the strain transport model to GAA MOSFETs which have different sidewall orientations depending on the channel direction. Drive current enhancement is the largest for the (001)/<110> case under large uniaxial tensile strain values exceeding 1%. In addition, we found that cross-sectional width of the nanosheet is a key parameter in maximizing the drive current for a given footprint. Optimization of device and strain configuration of single-stacked GAA devices is necessary to meet device performance specifications for sub-7nm technology.
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