Protection of Memories Suffering MCUs Through the Selection of the Optimal Interleaving Distance

Abstract

Interleaving, together with single error correction codes (SEC), are common techniques to protect memories against multiple cell upsets (MCUs). This kind of errors is increasingly important as technology scales, becoming a prominent effect, and therefore greatly affecting the reliability of memories. Ideally, the interleaving distance (ID) should be chosen as the maximum expected MCU size. In this way, all errors in an MCU would occur in different logical words, thus being correctable by the SEC codes. However, the use of large interleaving distances usually results in an area increase and a more complex design of memories. In this paper, the selection of the optimal interleaving distance is explored, keeping the area overhead and complexity as low as possible, without compromising memory reliability.