High speed recursion-free CORDIC architecture

Abstract

This paper proposes a novel unrolled CORDIC (Co-Ordinate Rotation DIgital Computer) architecture based on parallel operations of a series of micro-rotation stages in the conventional CORDIC. To improve the speed and lower the energy consumption, a Wallace tree reduction is used for the summation of the computed parallel terms. For a large number of micro-rotation stages, a first order approximation is used to reduce the complexity while maintaining the output data accuracy. The circuit has been implemented using a 65nm process. The results show a speed improvement of 20% and an energy-delay reduction of 27% with a minimal expense of 5% increase in the circuit area relative to a conventional CORDIC architecture. © 2010 IEEE.