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High speed recursion-free CORDIC architecture
- Issue Date
- Sep-2010
- Publisher
- IEEE
- Keywords
- Digital computers; Energy-delay; Co-ordinate rotation digital computers; Wallace tree; Rotation; Speed improvement; Output data; Parallel operations; Microrotation; Energy utilization; Computer architecture; First-order approximations
- Citation
- Proceedings - IEEE International SOC Conference, SOCC 2010, pp 65 - 70
- Pages
- 6
- Indexed
- SCOPUS
- Journal Title
- Proceedings - IEEE International SOC Conference, SOCC 2010
- Start Page
- 65
- End Page
- 70
- ISSN
- 2164-1676
2164-1706
- Abstract
- This paper proposes a novel unrolled CORDIC (Co-Ordinate Rotation DIgital Computer) architecture based on parallel operations of a series of micro-rotation stages in the conventional CORDIC. To improve the speed and lower the energy consumption, a Wallace tree reduction is used for the summation of the computed parallel terms. For a large number of micro-rotation stages, a first order approximation is used to reduce the complexity while maintaining the output data accuracy. The circuit has been implemented using a 65nm process. The results show a speed improvement of 20% and an energy-delay reduction of 27% with a minimal expense of 5% increase in the circuit area relative to a conventional CORDIC architecture. © 2010 IEEE.
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Related Researcher
- Nam, Hae woon
- ERICA 공학대학 (SCHOOL OF ELECTRICAL ENGINEERING)