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A Physics-Based Compact Model of III-V FETs for Digital Logic Applications: Current-Voltage and Capacitance-Voltage Characteristics

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dc.contributor.authorOh, Saeroonter-
dc.contributor.authorWong, H. -S. Philip-
dc.date.accessioned2021-06-23T14:40:21Z-
dc.date.available2021-06-23T14:40:21Z-
dc.date.created2021-01-21-
dc.date.issued2009-12-
dc.identifier.issn0018-9383-
dc.identifier.urihttps://scholarworks.bwise.kr/erica/handle/2021.sw.erica/40636-
dc.description.abstractA physics-based analytical compact model of InGaAs field-effect transistors (FETs) for digital logic applications is developed. This model neither heavily depends on parameter extraction nor requires any time-consuming computation while capturing the essential physics, enabling digital circuit design and circuit-level performance estimation for III-V FETs. The model captures short channel effects, trapezoidal-shape quantum-well energies, bias-dependent ballistic ratios, and capacitances including 2-D potential profile information. Each is verified via numerical calculations and 2-D electrostatic simulation, followed by a comparison of the model I-V characteristics with experiment data. Finally, the transient response of FO4 inverters demonstrates the use of the compact model for future technology circuit simulations.-
dc.language영어-
dc.language.isoen-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleA Physics-Based Compact Model of III-V FETs for Digital Logic Applications: Current-Voltage and Capacitance-Voltage Characteristics-
dc.typeArticle-
dc.contributor.affiliatedAuthorOh, Saeroonter-
dc.identifier.doi10.1109/TED.2009.2033411-
dc.identifier.scopusid2-s2.0-84859893394-
dc.identifier.wosid000271951700006-
dc.identifier.bibliographicCitationIEEE TRANSACTIONS ON ELECTRON DEVICES, v.56, no.12, pp.2917 - 2924-
dc.relation.isPartOfIEEE TRANSACTIONS ON ELECTRON DEVICES-
dc.citation.titleIEEE TRANSACTIONS ON ELECTRON DEVICES-
dc.citation.volume56-
dc.citation.number12-
dc.citation.startPage2917-
dc.citation.endPage2924-
dc.type.rimsART-
dc.type.docTypeArticle-
dc.description.journalClass1-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalResearchAreaPhysics-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.relation.journalWebOfScienceCategoryPhysics, Applied-
dc.subject.keywordPlusSCATTERING-
dc.subject.keywordPlusMOBILITY-
dc.subject.keywordPlusSIMULATION-
dc.subject.keywordPlusCHANNEL-
dc.subject.keywordPlusMOSFETS-
dc.subject.keywordPlusDEVICE-
dc.subject.keywordPlusLENGTH-
dc.subject.keywordPlusSPEED-
dc.subject.keywordAuthorCompact model-
dc.subject.keywordAuthordigital logic-
dc.subject.keywordAuthorIII-V field-effect transistor (FET)-
dc.subject.keywordAuthorInGaAs-
dc.identifier.urlhttps://ieeexplore.ieee.org/document/5306171-
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