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A Physics-Based Compact Model of III-V FETs for Digital Logic Applications: Current-Voltage and Capacitance-Voltage Characteristics

Authors
Oh, SaeroonterWong, H. -S. Philip
Issue Date
Dec-2009
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Keywords
Compact model; digital logic; III-V field-effect transistor (FET); InGaAs
Citation
IEEE TRANSACTIONS ON ELECTRON DEVICES, v.56, no.12, pp.2917 - 2924
Indexed
SCIE
SCOPUS
Journal Title
IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume
56
Number
12
Start Page
2917
End Page
2924
URI
https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/40636
DOI
10.1109/TED.2009.2033411
ISSN
0018-9383
Abstract
A physics-based analytical compact model of InGaAs field-effect transistors (FETs) for digital logic applications is developed. This model neither heavily depends on parameter extraction nor requires any time-consuming computation while capturing the essential physics, enabling digital circuit design and circuit-level performance estimation for III-V FETs. The model captures short channel effects, trapezoidal-shape quantum-well energies, bias-dependent ballistic ratios, and capacitances including 2-D potential profile information. Each is verified via numerical calculations and 2-D electrostatic simulation, followed by a comparison of the model I-V characteristics with experiment data. Finally, the transient response of FO4 inverters demonstrates the use of the compact model for future technology circuit simulations.
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COLLEGE OF ENGINEERING SCIENCES > SCHOOL OF ELECTRICAL ENGINEERING > 1. Journal Articles

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