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Parallel test method for NoC-based SoCs
- Issue Date
- Nov-2009
- Publisher
- IEEE
- Keywords
- Scheduling methods; NoC architectures; VLSI circuits; Routers; Multicasts; Programmable logic controllers; Best-effort services; Test time reduction; In-order packet delivery; Benchmark circuit; On chips; Parallel test; Microprocessor chips; Test access m
- Citation
- IEEE Conference ISOCC, pp.116 - 119
- Indexed
- OTHER
- Journal Title
- IEEE Conference ISOCC
- Start Page
- 116
- End Page
- 119
- Abstract
- Reusing on-chip functional interconnects as test access mechanism (TAM) appeared usual these days. One of the most important functional interconnects for highly crowded future system-on-chips (SoCs) is network-on-chip (NoC). Several NoC architectures including router and network interface (NI) have been proposed. They allow narrowcast and multicast of packets, in-order packet delivery, guaranteed throughput and best-effort services. Exploiting the preceding research, we present here a parallel test method and a manipulated scheduling method for NoC-based SoCs, while reusing NoC as TAM, with the goal of reducing overall test time. The proposed test method is compared with previous works using some of ITC'02 benchmark circuits which showed significant test time reduction. ©2009 IEEE.
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