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A 0.6-V Delta-Sigma Modulator With Subthreshold-Leakage Suppression Switches

Authors
Roh, HyungdongKim, HyoungjoongChoi, YoungkilRoh, JeongjinKim, Yi-GyeongKwon, Jong-Kee
Issue Date
Nov-2009
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Keywords
Analog-to-digital converter (ADC); delta-sigma modulator; harmonic distortion; leakage current; signal-to-noise-plus-distortion ratio (SNDR); switched-capacitor circuit
Citation
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.56, no.11, pp 825 - 829
Pages
5
Indexed
SCIE
SCOPUS
Journal Title
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
Volume
56
Number
11
Start Page
825
End Page
829
URI
https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/40747
DOI
10.1109/TCSII.2009.2032444
ISSN
1549-7747
1558-3791
Abstract
A 0.6-V 34-mu W delta-sigma modulator implemented by using a standard 0.13-mu m complementary metal-oxide-semiconductor technology is presented. This brief analyzes a subthreshold-leakage current problem in switched-capacitor circuits and proposes subthreshold-leakage suppression switches to solve the problem. To verify the operation of the subthreshold-leakage suppression switches, two different fifth-order delta-sigma modulators are implemented with conventional switches and new switches. The input feedforward architecture is used to reduce the voltage swings of the integrators. A high-performance low-quiescent amplifier architecture is developed for the modulator. The modulator, with new switches, achieves a dynamic range of 83 dB, a peak signal-to-noise ratio of 82 dB, and a peak signal-to-noise-plus-distortion ratio of 81 dB in a signal bandwidth of 20 kHz. The power consumption is 34 mu W for the modulator, and the core chip size is 0.33 mm(2).
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Roh, Jeong jin
ERICA 공학대학 (SCHOOL OF ELECTRICAL ENGINEERING)
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