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다층 배선 비아(Via)의 고주파 측정 기반 회로 모델링
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 김혜원 | - |
| dc.contributor.author | 김동철 | - |
| dc.contributor.author | 어영선 | - |
| dc.date.accessioned | 2021-06-23T15:07:00Z | - |
| dc.date.available | 2021-06-23T15:07:00Z | - |
| dc.date.created | 2021-02-18 | - |
| dc.date.issued | 2009-07 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/41047 | - |
| dc.description.abstract | A via is experimentally characterized by using high-frequency s-parameter measurements. Test patterns are designed and fabricated by using a package process. They are measured by using VNA (vector network analyzer) up to 25GHz. The parasitic effects due to access lines for on-wafer probing are deembedded. Then modeling the via as T-type circuit, the circuit model parameters are determined. It is shown that the proposed technique has excellent agreement with the measured s-parameters. | - |
| dc.language | 한국어 | - |
| dc.language.iso | ko | - |
| dc.publisher | 대한전자공학회 | - |
| dc.title | 다층 배선 비아(Via)의 고주파 측정 기반 회로 모델링 | - |
| dc.title.alternative | Circuit Modeling of Multi-Layer Interconnect Via based on High Frequency Measurement | - |
| dc.type | Article | - |
| dc.contributor.affiliatedAuthor | 어영선 | - |
| dc.identifier.bibliographicCitation | 2009년도 대한전자공학회 하계종합학술대회, pp.407 - 408 | - |
| dc.relation.isPartOf | 2009년도 대한전자공학회 하계종합학술대회 | - |
| dc.citation.title | 2009년도 대한전자공학회 하계종합학술대회 | - |
| dc.citation.startPage | 407 | - |
| dc.citation.endPage | 408 | - |
| dc.type.rims | ART | - |
| dc.description.journalClass | 3 | - |
| dc.description.isOpenAccess | N | - |
| dc.description.journalRegisteredClass | other | - |
| dc.identifier.url | https://www.dbpia.co.kr/journal/articleDetail?nodeId=NODE01381168 | - |
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Related Researcher
- EO, YUNG SEON
- ERICA 공학대학 (SCHOOL OF ELECTRICAL ENGINEERING)