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Technology Projection Using Simple Compact Models

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dc.contributor.authorWong, H-S. Philip-
dc.contributor.authorWei, Lan-
dc.contributor.authorOh, Saeroonter-
dc.contributor.authorLin, Albert-
dc.contributor.authorDeng, Jie-
dc.contributor.authorChong, Soogine-
dc.contributor.authorAkarvardar, Kerem-
dc.date.accessioned2021-06-23T16:38:55Z-
dc.date.available2021-06-23T16:38:55Z-
dc.date.issued2009-09-
dc.identifier.issn1946-1569-
dc.identifier.issn1946-1577-
dc.identifier.urihttps://scholarworks.bwise.kr/erica/handle/2021.sw.erica/41776-
dc.description.abstractWe review recent efforts to capture the device non-idealities for circuit-level technology projection for Si CMOS. We also give some examples of simple compact model development for assessing the circuit-level performance of exploratory devices such as III-V VET, carbon nanotube transistor, and nanoelectromechanical (NEM) transistors and relays.-
dc.format.extent8-
dc.language영어-
dc.language.isoENG-
dc.publisherIEEE-
dc.titleTechnology Projection Using Simple Compact Models-
dc.typeArticle-
dc.publisher.location미국-
dc.identifier.doi10.1109/SISPAD.2009.5290261-
dc.identifier.scopusid2-s2.0-74349109761-
dc.identifier.wosid000277103100001-
dc.identifier.bibliographicCitationInternational Conference on Simulation of Semiconductor Processes and Devices, SISPAD, pp 1 - 8-
dc.citation.titleInternational Conference on Simulation of Semiconductor Processes and Devices, SISPAD-
dc.citation.startPage1-
dc.citation.endPage8-
dc.type.docTypeProceedings Paper-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaComputer Science-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalWebOfScienceCategoryComputer Science, Theory & Methods-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.subject.keywordPlusNANOELECTROMECHANICAL LOGIC-
dc.subject.keywordPlusPERFORMANCE-
dc.subject.keywordAuthorTechnology projection-
dc.subject.keywordAuthorcompact model-
dc.subject.keywordAuthorIII-V FET-
dc.subject.keywordAuthorCNT-
dc.subject.keywordAuthorcarbon nanotube transistor-
dc.subject.keywordAuthornanoelectromechanical relay-
dc.subject.keywordAuthorNEMS-
dc.subject.keywordAuthorparasitic capacitance-
dc.subject.keywordAuthorparasitic resistance-
dc.subject.keywordAuthorSi CMOS-
dc.identifier.urlhttps://ieeexplore.ieee.org/document/5290261?arnumber=5290261&SID=EBSCO:edseee-
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