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Technology Projection Using Simple Compact Models
- Authors
- Wong, H-S. Philip; Wei, Lan; Oh, Saeroonter; Lin, Albert; Deng, Jie; Chong, Soogine; Akarvardar, Kerem
- Issue Date
- Sep-2009
- Publisher
- IEEE
- Keywords
- Technology projection; compact model; III-V FET; CNT; carbon nanotube transistor; nanoelectromechanical relay; NEMS; parasitic capacitance; parasitic resistance; Si CMOS
- Citation
- International Conference on Simulation of Semiconductor Processes and Devices, SISPAD, pp 1 - 8
- Pages
- 8
- Indexed
- SCIE
SCOPUS
- Journal Title
- International Conference on Simulation of Semiconductor Processes and Devices, SISPAD
- Start Page
- 1
- End Page
- 8
- ISSN
- 1946-1569
1946-1577
- Abstract
- We review recent efforts to capture the device non-idealities for circuit-level technology projection for Si CMOS. We also give some examples of simple compact model development for assessing the circuit-level performance of exploratory devices such as III-V VET, carbon nanotube transistor, and nanoelectromechanical (NEM) transistors and relays.
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