Logical Operation Based Parallel Decoding Scheme for H.264/AVC CAVLC
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 신현철 | - |
dc.date.accessioned | 2021-06-23T19:05:22Z | - |
dc.date.available | 2021-06-23T19:05:22Z | - |
dc.date.created | 2021-02-18 | - |
dc.date.issued | 2007-10 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/43411 | - |
dc.description.abstract | An effective parallel decoding method has been developed for context-based adaptive variable length coding (CAVLC). Several new ideas have been devised for scalable parallel processing, less area, and less power. First, simplified logical operations are used for fast low power operations, while table look-ups are used for many conventional CAVLC algorithms. Second the codes are grouped based on their lengths for efficient logical operation. Third, up to M bits of input is simultaneously analyzed. When M is large, decoding rate becomes high at a high area cost. For comparison, we have designed the logical operation based parallel decoder for M=8 and a typical conventional method based decoder. For similar decoding rates, our new approach uses 44% less area than the typical conventional method. | - |
dc.publisher | 대한전자공학회 | - |
dc.title | Logical Operation Based Parallel Decoding Scheme for H.264/AVC CAVLC | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | 신현철 | - |
dc.identifier.bibliographicCitation | International SoC Design Conference | - |
dc.relation.isPartOf | International SoC Design Conference | - |
dc.citation.title | International SoC Design Conference | - |
dc.type.rims | ART | - |
dc.description.journalClass | 3 | - |
dc.subject.keywordAuthor | H.264 | - |
dc.subject.keywordAuthor | CAVLC | - |
dc.subject.keywordAuthor | VLD | - |
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