Design of Digital Decimation Filter for Delta-Sigma A/D Converters
- Authors
- Roh, Hyungdong; Byun , Sanho; Ryu, Seongyoung; Choi, Youngkil; Nam, Hyunseok; Roh, Jeongjin
- Issue Date
- Jul-2007
- Publisher
- 대한전자공학회
- Citation
- International Technical Conference on Circuits/Systems, Computers and Communications, pp 645 - 646
- Pages
- 2
- Indexed
- OTHER
- Journal Title
- International Technical Conference on Circuits/Systems, Computers and Communications
- Start Page
- 645
- End Page
- 646
- URI
- https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/43559
- Abstract
- This paper presents details of the design and implementation of a fully synthesized digital decimation filter that provides time-to-market advantage for delta-sigma analog-todigital converters. This decimation filter is fabricated in 0.25-㎛ CMOS technology with 1.36 ㎡ of active area, and shows 4.4 ㎽ power consumption at a clock rate of 2.8224 ㎒. Experimental results show that this digital decimation filter is suitable for oversampled data converters and can be ported to new processes with fast redesign time since it does not have processdependent ROM or RAM circuits.
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- Appears in
Collections - COLLEGE OF ENGINEERING SCIENCES > SCHOOL OF ELECTRICAL ENGINEERING > 1. Journal Articles
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