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테스트 핀 축소에 의한 저비용 SoC 테스트 구조Reduced Pin-Count Test Architecture for Low-Cost SoC Test
- Other Titles
- Reduced Pin-Count Test Architecture for Low-Cost SoC Test
- Issue Date
- Jun-2007
- Publisher
- 한국테스트협회
- Citation
- 한국테스트학술대회
- Indexed
- OTHER
- Journal Title
- 한국테스트학술대회
- Abstract
- In this paper a reduced pin count SoC test architecture using IEEE 1149.1 and IEEE 1500 wrapper is presented. By using only a small number of test pins low cost automated test equipments (ATEs) can be efficiently utilized to SoC test cost. Experimental results show that the SoC test time can be significantly reduced by performing multi-site test.
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Collections - COLLEGE OF COMPUTING > SCHOOL OF COMPUTER SCIENCE > 1. Journal Articles
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