Scan-Chain 과 IEEE 1500 래퍼를 이용한 SoC 지연 고장 테스트

Abstract

With the increasing clock speeds and the decreasing feature sizes found in today’s nanometer designs, at-speed testing is a requirement to achieve high quality test results. This paper introduces the interface logic of available at-speed delay fault test, and proposes a test method using a proposed architecture. Experimental results evaluate the efficiency of the proposed method by comparing a fault coverage and the number of test patterns