Cost effective test planning for system-on-chip manufacture

Abstract

The test of chip has become an important issue as its complexity has been dramatically increased. Currently, system-on-chip (SoC) is major product that can be used for many applications. Since the SoC is a chip designed by VLSI design techniques, its methodologies of design and test are similar to conventional chip manufacturing aspects. However, the complexity, developing procedures, and many other things are different from the case of the conventional chips. Thus, new test approach is needed for complex SoC. The proposed economics model for SoC helps the chip developers predict total cost of SoC development at the early design stage, and decide the strategy to test by cost-effective way. © 2006 IEEE.