A New TWA based Efficient Signal Integrity Verification Technique for Non-Uniform RLC Interconnect Lines
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Jo, Chanmin | - |
dc.contributor.author | Kim, Hyunsik | - |
dc.contributor.author | Shin, Seongkyun | - |
dc.contributor.author | Eo, Yungseon | - |
dc.contributor.author | Shim, Jongin | - |
dc.date.accessioned | 2021-06-23T23:38:10Z | - |
dc.date.available | 2021-06-23T23:38:10Z | - |
dc.date.issued | 2005-05 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/45962 | - |
dc.description.abstract | A new TWA-based signal integrity verification technique for practical layout structures which are composed of non-uniform RLC lines with various discontinuities is presented. Transforming the non-uniform lines into virtual uniform lines, signal integrity of the practical layout structures can be very efficiently estimated by using the TWA-technique. It is shown that the proposed technique can estimate the signal integrity much more efficiently than generic SPICE model within 5% error. | - |
dc.format.extent | 5 | - |
dc.language | 한국어 | - |
dc.language.iso | KOR | - |
dc.publisher | 대한전자공학회 | - |
dc.title | A New TWA based Efficient Signal Integrity Verification Technique for Non-Uniform RLC Interconnect Lines | - |
dc.type | Article | - |
dc.publisher.location | 대한민국 | - |
dc.identifier.bibliographicCitation | 대한전자공학회 학술대회, pp 195 - 199 | - |
dc.citation.title | 대한전자공학회 학술대회 | - |
dc.citation.startPage | 195 | - |
dc.citation.endPage | 199 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | other | - |
dc.subject.keywordAuthor | interconnect | - |
dc.subject.keywordAuthor | non-uniform | - |
dc.subject.keywordAuthor | inductance | - |
dc.subject.keywordAuthor | signal integrity | - |
dc.subject.keywordAuthor | TWA | - |
dc.identifier.url | https://www.dbpia.co.kr/journal/articleDetail?nodeId=NODE01731668 | - |
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