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A Power Supply Rejection Compensated External Capacitor-Less Low Drop-Out Regulator
- Authors
- Guo, Tian; Moon, Jiho; Roh, Jeongjin
- Issue Date
- Oct-2019
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Keywords
- external capacitor-less LDO; power management integrated circuit (PMIC); PSR compensated LDO
- Citation
- Proceedings - 2019 International SoC Design Conference, ISOCC 2019, pp 54 - 55
- Pages
- 2
- Indexed
- SCOPUS
- Journal Title
- Proceedings - 2019 International SoC Design Conference, ISOCC 2019
- Start Page
- 54
- End Page
- 55
- ISSN
- 2163-9612
- Abstract
- This paper presents a compensation technique for a power supply rejection (PSR) improved external capacitor-less low drop-out (LDO) regulator. A replica circuit is used to cancel the power supply noise generated by the gate-source parasitic capacitor of the pass transistor. This design was fabricated in a 0.18 μm bipolar-CMOS-DMOS (BCD) technology with a power supply of 1.8 V. The active core chip area is 0.023 mm2, and the entire proposed LDO consumes 65 μA of quiescent current. It has a drop-out voltage of 200 mV, and the maximum load current is 60 mA. The measured PSR has a maximum-22 dB enhancement compared with a conventional uncompensated LDO when delivering a current of 60 mA. © 2019 IEEE.
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Related Researcher
- Roh, Jeong jin
- ERICA 공학대학 (SCHOOL OF ELECTRICAL ENGINEERING)