A compact multilayer IC package model for efficient simulation, analysis, and design of high-performance VLSI circuits
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Eo, Yungseon | - |
dc.contributor.author | Eisenstadt, WR | - |
dc.contributor.author | Jin, Woojin | - |
dc.contributor.author | Choi, Jinwoo | - |
dc.contributor.author | Shim, Jongin | - |
dc.date.accessioned | 2021-06-24T00:42:25Z | - |
dc.date.available | 2021-06-24T00:42:25Z | - |
dc.date.created | 2021-01-21 | - |
dc.date.issued | 2003-11 | - |
dc.identifier.issn | 1521-3323 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/46656 | - |
dc.description.abstract | A multilayered integrated circuit (IC) package structure is composed of many signal layers, power layers, and ground layers. Particularly, the whole planes are assigned for the power and ground of the system. Accordingly, the generic circuit representation of such a complicated multilayer IC package becomes too complicated to efficiently evaluate its electrical performance. In this work, a novel compact package circuit model for the efficient simulation and analysis of such complicated IC packages is presented. Unlike the conventional models, current distributions within the package are modeled by introducing a compact partial plane circuit model. Thus, the proposed package model is much simpler than the conventional generic circuit models, while its accuracy is preserved. Thereby, today's complicated IC packages can be efficiently evaluated and analyzed. Its accuracy and efficiency are verified by benchmarking it with a conventional generic package circuit model; this conventional model may not be practical to use for package evaluation and analysis. It is then shown that the proposed model can be efficiently applied for the signal integrity verification of complicated IC packages and high-performance VLSI circuits. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | Institute of Electrical and Electronics Engineers | - |
dc.title | A compact multilayer IC package model for efficient simulation, analysis, and design of high-performance VLSI circuits | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Eo, Yungseon | - |
dc.contributor.affiliatedAuthor | Shim, Jongin | - |
dc.identifier.doi | 10.1109/TADVP.2003.821093 | - |
dc.identifier.scopusid | 2-s2.0-0742303707 | - |
dc.identifier.wosid | 000188223000007 | - |
dc.identifier.bibliographicCitation | IEEE Transactions on Advanced Packaging, v.26, no.4, pp.392 - 401 | - |
dc.relation.isPartOf | IEEE Transactions on Advanced Packaging | - |
dc.citation.title | IEEE Transactions on Advanced Packaging | - |
dc.citation.volume | 26 | - |
dc.citation.number | 4 | - |
dc.citation.startPage | 392 | - |
dc.citation.endPage | 401 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Materials Science | - |
dc.relation.journalWebOfScienceCategory | Engineering, Manufacturing | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Materials Science, Multidisciplinary | - |
dc.subject.keywordPlus | SIMULTANEOUS SWITCHING NOISE | - |
dc.subject.keywordPlus | OFF-CHIP DRIVER | - |
dc.subject.keywordPlus | HIGH-SPEED | - |
dc.subject.keywordPlus | TIME CONSIDERATIONS | - |
dc.subject.keywordPlus | CMOS DRIVERS | - |
dc.subject.keywordPlus | MICROPROCESSOR | - |
dc.subject.keywordPlus | COMPUTATION | - |
dc.subject.keywordAuthor | circuit model | - |
dc.subject.keywordAuthor | ground plane | - |
dc.subject.keywordAuthor | IC package | - |
dc.subject.keywordAuthor | multilayer package | - |
dc.subject.keywordAuthor | partial plane model | - |
dc.subject.keywordAuthor | power plane | - |
dc.subject.keywordAuthor | signal integriy | - |
dc.subject.keywordAuthor | simultaneous switching noise | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/1257434/ | - |
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.
55 Hanyangdeahak-ro, Sangnok-gu, Ansan, Gyeonggi-do, 15588, Korea+82-31-400-4269 sweetbrain@hanyang.ac.kr
COPYRIGHT © 2021 HANYANG UNIVERSITY. ALL RIGHTS RESERVED.
Certain data included herein are derived from the © Web of Science of Clarivate Analytics. All rights reserved.
You may not copy or re-distribute this material in whole or in part without the prior written consent of Clarivate Analytics.