A new on-chip interconnect crosstalk model and experimental verification fur CMOS VLSI circuit design
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Eo, Yungseon | - |
dc.contributor.author | Eisenstadt, W.R. | - |
dc.contributor.author | Jeong, Ju young | - |
dc.contributor.author | Kwon, Oh kyong | - |
dc.date.accessioned | 2021-06-24T01:07:25Z | - |
dc.date.available | 2021-06-24T01:07:25Z | - |
dc.date.created | 2021-01-21 | - |
dc.date.issued | 2000-01 | - |
dc.identifier.issn | 0018-9383 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/46975 | - |
dc.description.abstract | A new, simple closed-form crosstalk model is proposed. The model is based on a lumped configuration but effectively includes the distributed properties of interconnect capacitance and resistance, CMOS device nonlinearity is simply approximated asa linear device. That is, the CMOS gate is modeled as a resistance at the driving port and a capacitance at a driven port. Interconnects are modeled as effective resistances and capacitances to match the distributed transmission behavior. The new model shows excellent agreement with SPICE simulations. Further, while existing models do not support the multiple line crosstalk behaviors, our model can be generalized to multiple lines. That is,unlike previously published work, even if the geometrical structures are not identical, it can accurately predict crosstalk. The model is experimentally verified with 0.35-mu m CMOS process-based interconnect test structures. The new model can be readily implemented in CAD analysis tools, Thereby, this model can be used to predict the signal integrity for high-speed and high-density VLSI circuit design. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A new on-chip interconnect crosstalk model and experimental verification fur CMOS VLSI circuit design | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Eo, Yungseon | - |
dc.identifier.doi | 10.1109/16.817578 | - |
dc.identifier.scopusid | 2-s2.0-0033888853 | - |
dc.identifier.wosid | 000084717800018 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON ELECTRON DEVICES, v.47, no.1, pp.129 - 140 | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON ELECTRON DEVICES | - |
dc.citation.title | IEEE TRANSACTIONS ON ELECTRON DEVICES | - |
dc.citation.volume | 47 | - |
dc.citation.number | 1 | - |
dc.citation.startPage | 129 | - |
dc.citation.endPage | 140 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.subject.keywordPlus | INTEGRATED-CIRCUITS | - |
dc.subject.keywordPlus | DELAY | - |
dc.subject.keywordPlus | NETWORKS | - |
dc.subject.keywordPlus | LINES | - |
dc.subject.keywordAuthor | crosstalk | - |
dc.subject.keywordAuthor | distributed-model | - |
dc.subject.keywordAuthor | effective-capacitance | - |
dc.subject.keywordAuthor | effective-resistance | - |
dc.subject.keywordAuthor | interconnects | - |
dc.subject.keywordAuthor | lumped-model | - |
dc.subject.keywordAuthor | signal-integrity | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/817578 | - |
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.
55 Hanyangdeahak-ro, Sangnok-gu, Ansan, Gyeonggi-do, 15588, Korea+82-31-400-4269 sweetbrain@hanyang.ac.kr
COPYRIGHT © 2021 HANYANG UNIVERSITY. ALL RIGHTS RESERVED.
Certain data included herein are derived from the © Web of Science of Clarivate Analytics. All rights reserved.
You may not copy or re-distribute this material in whole or in part without the prior written consent of Clarivate Analytics.