COMBINED HIERARCHICAL PLACEMENT ALGORITHM FOR ROW-BASED LAYOUTS
- Authors
- KIM, C; KIM, W; SHIN, H; RHEE, K; CHUNG, H; KIM, J
- Issue Date
- Aug-1993
- Publisher
- IEE-INST ELEC ENG
- Keywords
- ALGORITHMS; CIRCUIT LAYOUT CAD; SIMULATED ANNEALING
- Citation
- ELECTRONICS LETTERS, v.29, no.17, pp.1508 - 1509
- Indexed
- SCIE
SCOPUS
- Journal Title
- ELECTRONICS LETTERS
- Volume
- 29
- Number
- 17
- Start Page
- 1508
- End Page
- 1509
- URI
- https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/47074
- DOI
- 10.1049/el:19931005
- ISSN
- 0013-5194
- Abstract
- A hierarchial placement algorithm which combines mincut partitioning and simulated annealing has been developed. The objective of mincut partitioning is to minimise the number of crossing nets, while the objective of placement by simulated annealing is usually to minimise the total estimated wire length. The combined placement algorithm can optimise both the routing density and the estimated wire length. For efficiency, the placement is performed using multiple levels of hierarchy in the top-down direction. Several standard-cell and sea-of-gates (SOG) circuits are placed using this algorithm and promising results am obtained.
- Files in This Item
-
Go to Link
- Appears in
Collections - COLLEGE OF ENGINEERING SCIENCES > SCHOOL OF ELECTRICAL ENGINEERING > 1. Journal Articles

Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.