Time-Multiplexed 1687-Network for Test Cost Reduction
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Ansari, Muhammad Adil | - |
dc.contributor.author | Jung, Jihun | - |
dc.contributor.author | Kim, Dooyoung | - |
dc.contributor.author | Park, Sungju | - |
dc.date.accessioned | 2021-06-22T11:42:17Z | - |
dc.date.available | 2021-06-22T11:42:17Z | - |
dc.date.created | 2021-01-21 | - |
dc.date.issued | 2018-08 | - |
dc.identifier.issn | 0278-0070 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/5740 | - |
dc.description.abstract | The reconfigurable scan network standardized by IEEE std. 1687 offers flexibility in accessing the on-chip instruments, which significantly improves the test cost. In this paper, we present a novel time-multiplexed 1687-network architecture that significantly improves the absolute test application time of systems-on-chip at wafer-level as well as package-levels tests. This architecture leverages: 1) the ever increasing tester channel frequency; 2) the allowed test frequencies at the two test levels; and 3) the flexibility offered by the 1687-network. We also present a test-time calculation method for the proposed network architecture and use it in our experiments. Furthermore, we study the effects of the number of time slots on different parameters. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Time-Multiplexed 1687-Network for Test Cost Reduction | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Park, Sungju | - |
dc.identifier.doi | 10.1109/TCAD.2017.2766146 | - |
dc.identifier.scopusid | 2-s2.0-85032446527 | - |
dc.identifier.wosid | 000439381700013 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.37, no.8, pp.1681 - 1691 | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | - |
dc.citation.title | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | - |
dc.citation.volume | 37 | - |
dc.citation.number | 8 | - |
dc.citation.startPage | 1681 | - |
dc.citation.endPage | 1691 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Interdisciplinary Applications | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | SYSTEM-ON-CHIP | - |
dc.subject.keywordPlus | TEST ACCESS MECHANISM | - |
dc.subject.keywordPlus | POWER CONSTRAINTS | - |
dc.subject.keywordPlus | IEEE P1687 | - |
dc.subject.keywordPlus | OPTIMIZATION | - |
dc.subject.keywordPlus | DESIGN | - |
dc.subject.keywordPlus | SOCS | - |
dc.subject.keywordPlus | WRAPPER | - |
dc.subject.keywordAuthor | Design-for-testability | - |
dc.subject.keywordAuthor | IEEE std 1687 | - |
dc.subject.keywordAuthor | package-level test | - |
dc.subject.keywordAuthor | scan test | - |
dc.subject.keywordAuthor | time division multiplexing | - |
dc.subject.keywordAuthor | wafer-level test | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/8081843 | - |
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