Time-Multiplexed 1687-Network for Test Cost Reduction
- Authors
- Ansari, Muhammad Adil; Jung, Jihun; Kim, Dooyoung; Park, Sungju
- Issue Date
- Aug-2018
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Design-for-testability; IEEE std 1687; package-level test; scan test; time division multiplexing; wafer-level test
- Citation
- IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.37, no.8, pp.1681 - 1691
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
- Volume
- 37
- Number
- 8
- Start Page
- 1681
- End Page
- 1691
- URI
- https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/5740
- DOI
- 10.1109/TCAD.2017.2766146
- ISSN
- 0278-0070
- Abstract
- The reconfigurable scan network standardized by IEEE std. 1687 offers flexibility in accessing the on-chip instruments, which significantly improves the test cost. In this paper, we present a novel time-multiplexed 1687-network architecture that significantly improves the absolute test application time of systems-on-chip at wafer-level as well as package-levels tests. This architecture leverages: 1) the ever increasing tester channel frequency; 2) the allowed test frequencies at the two test levels; and 3) the flexibility offered by the 1687-network. We also present a test-time calculation method for the proposed network architecture and use it in our experiments. Furthermore, we study the effects of the number of time slots on different parameters.
- Files in This Item
-
Go to Link
- Appears in
Collections - COLLEGE OF COMPUTING > SCHOOL OF COMPUTER SCIENCE > 1. Journal Articles
![qrcode](https://api.qrserver.com/v1/create-qr-code/?size=55x55&data=https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/5740)
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.