300 mA LDO Using 0.94 mu A I-Q With an Additional Feedback Path for Buffer Turn-off Under Light-Load Conditions
- Authors
- Jeon, Inho; Guo, Tian; Roh, Jeongjin
- Issue Date
- Mar-2021
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- LDO regulator; DO-OTA; adaptive biasing; dynamic biasing; source follower; low-I-Q; power management integrated circuit (PMIC)
- Citation
- IEEE ACCESS, v.9, pp 51784 - 51792
- Pages
- 9
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE ACCESS
- Volume
- 9
- Start Page
- 51784
- End Page
- 51792
- URI
- https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/624
- DOI
- 10.1109/ACCESS.2021.3069316
- ISSN
- 2169-3536
2169-3536
- Abstract
- This paper proposes a 300 mA low-dropout (LDO) regulator using an I-Q of only 0.94 mu A, which has the advantage of minimizing power consumption in the standby mode of a battery-based system. The LDO uses a source follower buffer with dynamic biasing to maintain loop stability and load transient response performance. Under light-load conditions, the buffer enters a fully-off state because there is a subnA bias current. Therefore, the LDO uses a dual output operational transconductance amplifier (DO-OTA) for operation under light-load conditions. The second output of the DO-OTA for light-load operation in the LDO forms an additional feedback path instead of the fully-off buffer. The second output of the DO-OTA is designed to consume a current lower than the bias current of the buffer while operating. Furthermore, the buffer in the LDO is designed for operation above 5 mA I-L. While the buffer is operating, the dynamic biasing current of the buffer is used as the second output of the DO-OTA. The second output of the DO-OTA has lower output impedance characteristics than its main output, so the LDO can secure loop stability under light-load conditions by lowering the DC gain. As a result, the LDO exhibits load transient response performance up to 300 mA by using a minimal I-Q under the no-load condition. The LDO is based on a 180 nm bipolar-CMOS-DMOS (BCDMOS) process and covers an area of approximately 256 x 143 mu m(2). The measured I-Q is 0.94 mu A under the no-load condition with a maximum load current of 300 mA.
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