Strain effect on performance of multi-stacked gate-all-around CMOS inverters

Abstract

We investigated the circuit performance of gate-all-around (GAA) CMOS inverters including strain for various sub-7 nm technology node device architectures. Multi-stacked GAA structure can compensate for the small cross-sectional area to increase the current drive per device footprint. However, due to the increase in parasitic capacitance, delay gain may be marginal. Nanosheets provide a large effective width per footprint and exhibits tolerance to parasitic components compared to nanowires. We show the logic performance of strained GAA CMOS for various number of stacked channel levels, strain conditions, and load capacitance conditions. Device simulations include quantum effects in the confined channel and strain-dependent multi-valley mobility models. Carrier mobility curves and current enhancement by strain are validated by comparison with experimental and advanced simulation results in the literature, respectively. Device combinations that effectively reduce the inverter delay, power-delay-product, and mitigate the asymmetric pull-up and pull-down delay are explored. Increasing the PMOS strain can improve the power-delay product of GAA CMOS inverters by 25 similar to 35%.