Simulation study on effect of drain underlap in gate-all-around tunneling field-effect transistors

Abstract

In this work, the effects of underlapping drain junction on the performances of gate-all-around (GAA) tunneling field-effect transistors (TFETs) have been studied in terms of direct-current (DC) characteristics including on-current (I-on), off-current (I-off), subthreshold swing (S), and I-on/I-off ratio. In addition, the dependences of intrinsic delay time (tau) and radio-frequency (RF) performances including cut-off frequency (f(T)) and maximum oscillation frequency (f(max)) on gate-drain capacitance (C-gd) with the underlapping were investigated as the gate length (L-gate) is scaled. A GAA TFET with asymmetric junctions, with an underlap at the drain side, demonstrated DC and RF performances superior to those of a device with symmetric junctions. (C) 2013 Elsevier B.V. All rights reserved.