Simulation study on effect of drain underlap in gate-all-around tunneling field-effect transistors
- Authors
- Lee, Jae Sung; Seo, Jae Hwa; Cho, Seongjae; Lee, Jung-Hee; Kang, Shin-Won; Bae, Jin-Hyuk; Cho, Eou-Sik; Kang, In Man
- Issue Date
- Aug-2013
- Publisher
- ELSEVIER SCIENCE BV
- Keywords
- Gate-all-around (GAA); Tunneling field-effect transistor (TFET); Radio-frequency (RF); Asymmetric junctions; Drain underlap
- Citation
- CURRENT APPLIED PHYSICS, v.13, no.6, pp.1143 - 1149
- Journal Title
- CURRENT APPLIED PHYSICS
- Volume
- 13
- Number
- 6
- Start Page
- 1143
- End Page
- 1149
- URI
- https://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/14376
- DOI
- 10.1016/j.cap.2013.03.012
- ISSN
- 1567-1739
- Abstract
- In this work, the effects of underlapping drain junction on the performances of gate-all-around (GAA) tunneling field-effect transistors (TFETs) have been studied in terms of direct-current (DC) characteristics including on-current (I-on), off-current (I-off), subthreshold swing (S), and I-on/I-off ratio. In addition, the dependences of intrinsic delay time (tau) and radio-frequency (RF) performances including cut-off frequency (f(T)) and maximum oscillation frequency (f(max)) on gate-drain capacitance (C-gd) with the underlapping were investigated as the gate length (L-gate) is scaled. A GAA TFET with asymmetric junctions, with an underlap at the drain side, demonstrated DC and RF performances superior to those of a device with symmetric junctions. (C) 2013 Elsevier B.V. All rights reserved.
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