Investigation and Optimization of Double-gate MPI 1T DRAM with Gate-induced Drain Leakage Operation
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Ha, Jongmin | - |
dc.contributor.author | Lee, Jae Yoon | - |
dc.contributor.author | Kim, Myeongseon | - |
dc.contributor.author | Cho, Seongjae | - |
dc.contributor.author | Cho, Il Hwan | - |
dc.date.available | 2020-02-27T03:42:46Z | - |
dc.date.created | 2020-02-04 | - |
dc.date.issued | 2019-04 | - |
dc.identifier.issn | 1598-1657 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/1668 | - |
dc.description.abstract | In this paper, we propose a double-gate one-transistor dynamic random-access memory (1T DRAM) with middle partial insulation (MPI) structure for low power application. Low power operation with the gate-induced drain leakage (GIDL) programming method can be obtained while maintaining the original advantages of MPI 1T-DRAM. The optimization of the MPI 1T-DRAM device for the GIDL method is investigated with technology computer-aided design (TCAD). High current ratio and low power consumption are obtained from the proposed 1T-DRAM device. Optimal device design in terms of barrier insulator length and fin width have been carried out for improvements of device performances and reliability. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEK PUBLICATION CENTER | - |
dc.relation.isPartOf | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE | - |
dc.subject | LOW-POWER | - |
dc.subject | 1T-DRAM | - |
dc.title | Investigation and Optimization of Double-gate MPI 1T DRAM with Gate-induced Drain Leakage Operation | - |
dc.type | Article | - |
dc.type.rims | ART | - |
dc.description.journalClass | 1 | - |
dc.identifier.wosid | 000465573000004 | - |
dc.identifier.doi | 10.5573/JSTS.2019.19.2.165 | - |
dc.identifier.bibliographicCitation | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.19, no.2, pp.165 - 171 | - |
dc.identifier.kciid | ART002459015 | - |
dc.identifier.scopusid | 2-s2.0-85067037273 | - |
dc.citation.endPage | 171 | - |
dc.citation.startPage | 165 | - |
dc.citation.title | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE | - |
dc.citation.volume | 19 | - |
dc.citation.number | 2 | - |
dc.contributor.affiliatedAuthor | Lee, Jae Yoon | - |
dc.contributor.affiliatedAuthor | Cho, Seongjae | - |
dc.type.docType | Article | - |
dc.subject.keywordAuthor | 1T DRAM | - |
dc.subject.keywordAuthor | middle partial insulation | - |
dc.subject.keywordAuthor | gate-induced drain leakage (GIDL) | - |
dc.subject.keywordAuthor | TCAD | - |
dc.subject.keywordPlus | LOW-POWER | - |
dc.subject.keywordPlus | 1T-DRAM | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.description.journalRegisteredClass | kci | - |
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