Design and Electrical Characterization of 2-T Thyristor RAM With Low Power Consumption
DC Field | Value | Language |
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dc.contributor.author | Kim, Youngmin | - |
dc.contributor.author | Kwon, Min-Woo | - |
dc.contributor.author | Ryoo, Kyung-Chang | - |
dc.contributor.author | Cho, Seongjae | - |
dc.contributor.author | Park, Byung-Gook | - |
dc.date.available | 2020-02-27T11:42:07Z | - |
dc.date.created | 2020-02-06 | - |
dc.date.issued | 2018-03 | - |
dc.identifier.issn | 0741-3106 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/4031 | - |
dc.description.abstract | In this letter, a Si-based two-terminal (2-T) thyristor random-access memory (TRAM) device is designed and characterized, and its operation window and power consumption are closely investigated by technology computer-aided design (TCAD) simulation. The properly scaled 2-T TRAM device has higher reliability since it can rule out impact ionization. Write time (T-write) and erase time (T-erase) reach below 10 ns and zero energy is consumed to hold state achieving high competitiveness with the existing dynamic random-access memory (DRAM). The state current ratio reaches higher than 10(5). Also, V-write and erase voltage (V-erase) of the 2-T TRAM appear to be below 2 and -1.2 V, respectively, in the permissible operation window, with less energy consumption compared with the conventional ones. The 2-T TRAM is a strong candidate for capacitorless DRAM technology. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.relation.isPartOf | IEEE ELECTRON DEVICE LETTERS | - |
dc.subject | DRAM CELL | - |
dc.title | Design and Electrical Characterization of 2-T Thyristor RAM With Low Power Consumption | - |
dc.type | Article | - |
dc.type.rims | ART | - |
dc.description.journalClass | 1 | - |
dc.identifier.wosid | 000426794100007 | - |
dc.identifier.doi | 10.1109/LED.2018.2796139 | - |
dc.identifier.bibliographicCitation | IEEE ELECTRON DEVICE LETTERS, v.39, no.3, pp.355 - 358 | - |
dc.identifier.scopusid | 2-s2.0-85040906235 | - |
dc.citation.endPage | 358 | - |
dc.citation.startPage | 355 | - |
dc.citation.title | IEEE ELECTRON DEVICE LETTERS | - |
dc.citation.volume | 39 | - |
dc.citation.number | 3 | - |
dc.contributor.affiliatedAuthor | Kim, Youngmin | - |
dc.contributor.affiliatedAuthor | Cho, Seongjae | - |
dc.type.docType | Article | - |
dc.subject.keywordAuthor | Thyristor | - |
dc.subject.keywordAuthor | 2-T TRAM | - |
dc.subject.keywordAuthor | TCAD | - |
dc.subject.keywordAuthor | low power consumption | - |
dc.subject.keywordAuthor | operation window | - |
dc.subject.keywordAuthor | capacitorless DRAM | - |
dc.subject.keywordPlus | DRAM CELL | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
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