Design and Electrical Characterization of 2-T Thyristor RAM With Low Power Consumption
- Authors
- Kim, Youngmin; Kwon, Min-Woo; Ryoo, Kyung-Chang; Cho, Seongjae; Park, Byung-Gook
- Issue Date
- Mar-2018
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Thyristor; 2-T TRAM; TCAD; low power consumption; operation window; capacitorless DRAM
- Citation
- IEEE ELECTRON DEVICE LETTERS, v.39, no.3, pp.355 - 358
- Journal Title
- IEEE ELECTRON DEVICE LETTERS
- Volume
- 39
- Number
- 3
- Start Page
- 355
- End Page
- 358
- URI
- https://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/4031
- DOI
- 10.1109/LED.2018.2796139
- ISSN
- 0741-3106
- Abstract
- In this letter, a Si-based two-terminal (2-T) thyristor random-access memory (TRAM) device is designed and characterized, and its operation window and power consumption are closely investigated by technology computer-aided design (TCAD) simulation. The properly scaled 2-T TRAM device has higher reliability since it can rule out impact ionization. Write time (T-write) and erase time (T-erase) reach below 10 ns and zero energy is consumed to hold state achieving high competitiveness with the existing dynamic random-access memory (DRAM). The state current ratio reaches higher than 10(5). Also, V-write and erase voltage (V-erase) of the 2-T TRAM appear to be below 2 and -1.2 V, respectively, in the permissible operation window, with less energy consumption compared with the conventional ones. The 2-T TRAM is a strong candidate for capacitorless DRAM technology.
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