A Quantum-Well Charge-Trap Synaptic Transistor with Highly Linear Weight Tunability
DC Field | Value | Language |
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dc.contributor.author | Yu, E. | - |
dc.contributor.author | Cho, S. | - |
dc.contributor.author | Roy, K. | - |
dc.contributor.author | Park, B. | - |
dc.date.available | 2020-08-31T00:35:31Z | - |
dc.date.created | 2020-08-24 | - |
dc.date.issued | 2020-07 | - |
dc.identifier.issn | 2168-6734 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/78074 | - |
dc.description.abstract | In this work, a novel synaptic transistor has been proposed and analyzed through technology computer-aided design (TCAD) simulation. The proposed device has merits of full-Si processing compatibility, short-and long-term plasticity, high energy efficiency, and linear and symmetric conductance adjustability. The proposed device consists of a quantum-well structure and a charge-trap unit for realizing both short-and long-term memories, respectively. The quantum-well charge-trap synaptic transistor (QW CTS) employs two independent gates to separate inference and weight adjustment operation. An optimally designed and validated QW CTS has demonstrated a highly linear and symmetric weight tunability, with an ultra-low energy consumption of 1.5 fJ per synaptic event. The QW CTS can be a core element in the hardware-driven Si neuromorphic system. CCBY | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.relation.isPartOf | IEEE Journal of the Electron Devices Society | - |
dc.title | A Quantum-Well Charge-Trap Synaptic Transistor with Highly Linear Weight Tunability | - |
dc.type | Article | - |
dc.type.rims | ART | - |
dc.description.journalClass | 1 | - |
dc.identifier.wosid | 000559512700013 | - |
dc.identifier.doi | 10.1109/JEDS.2020.3011409 | - |
dc.identifier.bibliographicCitation | IEEE Journal of the Electron Devices Society, v.8, pp.836 - 840 | - |
dc.description.isOpenAccess | N | - |
dc.identifier.scopusid | 2-s2.0-85089454381 | - |
dc.citation.endPage | 840 | - |
dc.citation.startPage | 836 | - |
dc.citation.title | IEEE Journal of the Electron Devices Society | - |
dc.citation.volume | 8 | - |
dc.contributor.affiliatedAuthor | Cho, S. | - |
dc.type.docType | Article | - |
dc.subject.keywordAuthor | energy efficiency | - |
dc.subject.keywordAuthor | hardware-driven neuromorphic system. | - |
dc.subject.keywordAuthor | linear weight tunability | - |
dc.subject.keywordAuthor | Logic gates | - |
dc.subject.keywordAuthor | long-term plasticity (LTP) | - |
dc.subject.keywordAuthor | Mathematical model | - |
dc.subject.keywordAuthor | Neuromorphics | - |
dc.subject.keywordAuthor | quantum-well charge-trap synaptic transistor | - |
dc.subject.keywordAuthor | short-term plasticity (STP) | - |
dc.subject.keywordAuthor | Si-processing compatibility | - |
dc.subject.keywordAuthor | Silicon | - |
dc.subject.keywordAuthor | Silicon germanium | - |
dc.subject.keywordAuthor | Transistors | - |
dc.subject.keywordAuthor | Tunneling | - |
dc.subject.keywordPlus | Charge trapping | - |
dc.subject.keywordPlus | Electronic design automation | - |
dc.subject.keywordPlus | Energy efficiency | - |
dc.subject.keywordPlus | Energy utilization | - |
dc.subject.keywordPlus | Silicon | - |
dc.subject.keywordPlus | Adjustability | - |
dc.subject.keywordPlus | High energy efficiency | - |
dc.subject.keywordPlus | Long term memory | - |
dc.subject.keywordPlus | Neuromorphic systems | - |
dc.subject.keywordPlus | Quantum well structures | - |
dc.subject.keywordPlus | Synaptic events | - |
dc.subject.keywordPlus | Technology computer aided design | - |
dc.subject.keywordPlus | Ultra low energy | - |
dc.subject.keywordPlus | Semiconductor quantum wells | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
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