Detailed Information
Cited 10 time in 
Cited 10 time in 
Cited 10 time in
Metadata Downloads
A Quantum-Well Charge-Trap Synaptic Transistor with Highly Linear Weight Tunability
- Issue Date
- Jul-2020
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Keywords
- energy efficiency; hardware-driven neuromorphic system.; linear weight tunability; Logic gates; long-term plasticity (LTP); Mathematical model; Neuromorphics; quantum-well charge-trap synaptic transistor; short-term plasticity (STP); Si-processing compatibility; Silicon; Silicon germanium; Transistors; Tunneling
- Citation
- IEEE Journal of the Electron Devices Society, v.8, pp.836 - 840
- Journal Title
- IEEE Journal of the Electron Devices Society
- Volume
- 8
- Start Page
- 836
- End Page
- 840
- ISSN
- 2168-6734
- Abstract
- In this work, a novel synaptic transistor has been proposed and analyzed through technology computer-aided design (TCAD) simulation. The proposed device has merits of full-Si processing compatibility, short-and long-term plasticity, high energy efficiency, and linear and symmetric conductance adjustability. The proposed device consists of a quantum-well structure and a charge-trap unit for realizing both short-and long-term memories, respectively. The quantum-well charge-trap synaptic transistor (QW CTS) employs two independent gates to separate inference and weight adjustment operation. An optimally designed and validated QW CTS has demonstrated a highly linear and symmetric weight tunability, with an ultra-low energy consumption of 1.5 fJ per synaptic event. The QW CTS can be a core element in the hardware-driven Si neuromorphic system. CCBY
- Files in This Item
- There are no files associated with this item.
- Appears in
Collections - IT융합대학 > 전자공학과 > 1. Journal Articles
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.
Related Researcher
- Cho, Seong Jae
- IT (Major of Electronic Engineering)