Performance Improvement of 1T DRAM by Raised Source and Drain Engineering
- Authors
- Ansari, Md Hasan Raza; Cho, Seongjae
- Issue Date
- Apr-2021
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Keywords
- Double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET); Electric potential; Impact ionization; Logic gates; low-power operation; Mathematical model; MOSFET; one-transistor (1T) dynamic random access memory (DRAM); Random access memory; retention time; sensing margin (SM); Silicon; technology computer-aided design (TCAD).
- Citation
- IEEE Transactions on Electron Devices, v.68, no.4, pp.1577 - 1584
- Journal Title
- IEEE Transactions on Electron Devices
- Volume
- 68
- Number
- 4
- Start Page
- 1577
- End Page
- 1584
- URI
- https://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/80772
- DOI
- 10.1109/TED.2021.3056952
- ISSN
- 0018-9383
- Abstract
- In this work, a double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) with raised source and drain (RSD) regions is utilized for application of one-transistor (1T) dynamic random access memory (DRAM) through series of validation by technology computer-aided design (TCAD) device simulation. The engineered device shows less short-channel effects (SCEs) and unwanted interband tunneling compared with the usual DG MOSFETs. As a 1T DRAM device, it demonstrates longer retention time (Tret) and larger sensing margin (SM). The designed 1T DRAM achieves Tret ~330 and ~200 ms at 27 °C and 85 °C, respectively, at 50-nm channel length. Also, the device shows higher current ratio and consumes low power (84.7 nW for write ``1'') and energy (2.16 x 10⁻¹⁵ J for read ``1'' and 1.5 x 10⁻¹⁷ J for read ``0'' operations). Furthermore, it is revealed that low-κ spacer has an effect of increasing Tret in the device. IEEE
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