A Reusable Code-Based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks
- Authors
- Seo, Min-Jae; Roh, Yi-Ju; Chang, Dong-Jin; Kim, Wan; Kim, Ye-Dam; Ryu, Seung-Tak
- Issue Date
- Dec-2018
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Design methodology; successive approximation register (SAR) ADC; capacitor-DAC (CDAC) compiler; analog circuit synthesis; skewed NAND-based comparator; synthesizable bootstrapped switch; standard cell
- Citation
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.65, no.12, pp.1904 - 1908
- Journal Title
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
- Volume
- 65
- Number
- 12
- Start Page
- 1904
- End Page
- 1908
- URI
- https://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/83652
- DOI
- 10.1109/TCSII.2018.2822811
- ISSN
- 1549-7747
- Abstract
- This brief proposes a code-reusable design methodology for synthesizable successive approximation register (SAR) ADCs based on the digital design flow to significantly reduce design effort. The SAR ADCs are composed of a capacitor-DAC (CDAC) macro cell generated by a CDAC compiler and analog functional blocks implemented utilizing digital standard cells. Two prototypes of SAR ADCs (12-bit 100 kS/s and 11-bit 50 MS/s) are fabricated in different CMOS processes (180 nm and 28 nm). The prototype ADCs prove the effectiveness of the proposed design methodology with comparable performances with full-custom designed SAR ADCs.
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