Sub-10 nm Ge/GaAs Heterojunction-Based Tunneling Field-Effect Transistor with Vertical Tunneling Operation for Ultra-Low-Power Applications
- Authors
- Yoon, Young Jun; Seo, Jae Hwa; Cho, Seongjae; Kwon, Hyuck-In; Lee, Jung-Hee; Kang, In Man
- Issue Date
- Apr-2016
- Publisher
- IEEK PUBLICATION CENTER
- Keywords
- Tunneling field-effect transistor (TFET); low-power (LP) performance; short-channel effect (SCE); Ge/GaAs heterojunction; vertical tunneling operation
- Citation
- JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.16, no.2
- Journal Title
- JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
- Volume
- 16
- Number
- 2
- URI
- https://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/8441
- DOI
- 10.5573/JSTS.2016.16.2.172
- ISSN
- 1598-1657
- Abstract
- In this paper, we propose a sub-10 nm Ge/GaAs heterojunction-based tunneling field-effect transistor (TFET) with vertical band-to-band tunneling (BBT) operation for ultra-low-power (LP) applications. We design a stack structure that is based on the Ge/GaAs heterojunction to realize the vertical BBT operation. The use of vertical BBT operations in devices results in excellent subthreshold characteristics with a reduction in the drain-induced barrier thinning (DIBT) phenomenon. The proposed device with a channel length (L-ch) of 5 nm exhibits outstanding LP performance with a subthreshold swing (S) of 29.1 mV/dec and an off-state current (I-off) of 1.12 x 10(-11) A/mu m. In addition, the use of the high-k spacer dielectric HfO2 improves the on-state current (I-on) with an intrinsic delay time (tau) because of a higher fringing field. We demonstrate a sub-10 nm LP switching device that realizes a good S and lower Ioff at a lower supply voltage (V-DD) of 0.2 V.
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