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8.4-to-16-bit resolution, 1-to-16 kHz bandwidth ADC with programmable-gain functionality for multi-sensor applicationsopen access
- Issue Date
- Sep-2019
- Publisher
- INST ENGINEERING TECHNOLOGY-IET
- Keywords
- CMOS integrated circuits; analogue-digital conversion; low-power electronics; delta-sigma modulation; sensor fusion; modulators; multisensor system; bio-signals; PG NS SAR ADC; third-order delta-sigma modulator; programmable-gain first-order noise-shaping SAR ADC; PG first-order NS successive-approximation register analogue-to-digital converter; voltage 1; 8 V
- Citation
- ELECTRONICS LETTERS, v.55, no.18, pp.982 - 983
- Journal Title
- ELECTRONICS LETTERS
- Volume
- 55
- Number
- 18
- Start Page
- 982
- End Page
- 983
- ISSN
- 0013-5194
- Abstract
- A resolution-reconfigurable, bandwidth-scalable analogue-to-digital converter (ADC) with programmable-gain (PG) functionality for a multi-sensor system, which encompasses various signals such as bio-signals and battery-level, is presented. In PG and low-power mode, a PG first-order noise-shaping (NS) successive-approximation register (SAR) ADC achieves 8.4-to-10.2-bit operating up to 16 kHz while providing a gain of 1/2/4. The PG NS SAR ADC can be reconfigured as an adder and a quantiser in a delta-sigma (Delta sigma) modulator enhancing the order of the modulator for high-resolution. The third-order Delta sigma modulator achieves 16.1 bits in a bandwidth of 1 kHz. The work is implemented in a 0.18 mu m CMOS process with a 1.8 V power supply.
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