Silicon Nanowire Charge Trapping Memory for Energy-Efficient Neuromorphic Computing
- Authors
- Ansari, Md. Hasan Raza; Kannan, Udaya Mohanan; El-Atab, Nazek
- Issue Date
- Jul-2023
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Si-nanowire; gate all around (GAA); synaptic transistor; short term potentiation (STP); long term potentiation (LTP); long term depression (LTD); neural network; neuromorphic computing
- Citation
- IEEE TRANSACTIONS ON NANOTECHNOLOGY, v.22, pp.409 - 416
- Journal Title
- IEEE TRANSACTIONS ON NANOTECHNOLOGY
- Volume
- 22
- Start Page
- 409
- End Page
- 416
- URI
- https://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/88893
- DOI
- 10.1109/TNANO.2023.3296673
- ISSN
- 1536-125X
- Abstract
- This work highlights the utilization of the floating body effect and charge-trapping/de-trapping phenomenon of a Silicon-nanowire (Si-nanowire) charge-trapping memory for an artificial synapse of neuromorphic computing application. Charge trapping/de-trapping in the nitride layer characterizes the long-term potentiation (LTP)/depression (LTD). The accumulation of holes in the potential well achieves short-term potentiation (STP) and controls the transition from STP to LTP. Also, the transition from STP to LTP is analyzed through gate length scaling and high-? material (Al2O3) for blocking oxide. Furthermore, the conductance values of the device are utilized for system-level simulation. System-level hardware parameters of a convolutional neural network (CNN) for inference applications are evaluated and compared to a static random-access memory (SRAM) device and charge-trapping memory. The results confirm that the Si-nanowire transistor with better gate controllability has a high retention time for LTP states, consumes low power, and archives better accuracy (91.27%). These results make the device suitable for low-power neuromorphic applications.
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