An Area-Efficient Integrate-and-Fire Neuron Circuit with Enhanced Robustness against Synapse Variability in Hardware Neural Network
DC Field | Value | Language |
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dc.contributor.author | Shah, Arati Kumari | - |
dc.contributor.author | Udaya Mohanan, Kannan | - |
dc.contributor.author | Park, Jisun | - |
dc.contributor.author | Shin, Hyungsoon | - |
dc.contributor.author | Cho, Eou-Sik | - |
dc.contributor.author | Cho, Seongjae | - |
dc.date.accessioned | 2024-01-30T06:00:37Z | - |
dc.date.available | 2024-01-30T06:00:37Z | - |
dc.date.issued | 2023-12 | - |
dc.identifier.issn | 1751-858X | - |
dc.identifier.issn | 1751-8598 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/90243 | - |
dc.description.abstract | Neuron circuits are the fundamental building blocks in the modern neuromorphic system. Designing compact and low-power neuron circuits can significantly improve the overall area and energy efficiencies of a neuromorphic chip architecture. Here, practical neuron circuits must overcome the variations arising from nonideal behaviors of synaptic devices, such as stuck-at-fault and conductance deviation. In this study, a compact leaky integrate-and-fire neuron circuit has been designed, with resilience to synaptic device state variations, for hardware implementation of spiking neural networks (SNNs). The proposed neuron circuit is simulated on the 0.35-mu m Si complementary metal-oxide-semiconductor technology node by a series of circuit simulations based on HSPICE. The proposed circuit occupies a reduced area and exhibits low power consumption (14.7 mu W per spike). Furthermore, the optimized circuit design results in a high degree of tolerance toward input-current variations arising from conductance-state variations in the synapse array. Hence, the proposed neuron circuit would be capable of substantially improving the area efficiency and reliability in the realization of the hardware-oriented SNN architectures. | - |
dc.language | 영어 | - |
dc.language.iso | ENG | - |
dc.publisher | WILEY-HINDAWI | - |
dc.title | An Area-Efficient Integrate-and-Fire Neuron Circuit with Enhanced Robustness against Synapse Variability in Hardware Neural Network | - |
dc.type | Article | - |
dc.identifier.wosid | 001137288900001 | - |
dc.identifier.doi | 10.1049/2023/1052063 | - |
dc.identifier.bibliographicCitation | IET CIRCUITS DEVICES & SYSTEMS, v.2023 | - |
dc.description.isOpenAccess | Y | - |
dc.citation.title | IET CIRCUITS DEVICES & SYSTEMS | - |
dc.citation.volume | 2023 | - |
dc.type.docType | Article | - |
dc.publisher.location | 영국 | - |
dc.subject.keywordPlus | SPIKING NEURONS | - |
dc.subject.keywordPlus | MEMORY | - |
dc.subject.keywordPlus | MODEL | - |
dc.subject.keywordPlus | DEVICES | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
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