An Area-Efficient Integrate-and-Fire Neuron Circuit with Enhanced Robustness against Synapse Variability in Hardware Neural Networkopen access
- Authors
- Shah, Arati Kumari; Udaya Mohanan, Kannan; Park, Jisun; Shin, Hyungsoon; Cho, Eou-Sik; Cho, Seongjae
- Issue Date
- Dec-2023
- Publisher
- WILEY-HINDAWI
- Citation
- IET CIRCUITS DEVICES & SYSTEMS, v.2023
- Journal Title
- IET CIRCUITS DEVICES & SYSTEMS
- Volume
- 2023
- URI
- https://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/90243
- DOI
- 10.1049/2023/1052063
- ISSN
- 1751-858X
1751-8598
- Abstract
- Neuron circuits are the fundamental building blocks in the modern neuromorphic system. Designing compact and low-power neuron circuits can significantly improve the overall area and energy efficiencies of a neuromorphic chip architecture. Here, practical neuron circuits must overcome the variations arising from nonideal behaviors of synaptic devices, such as stuck-at-fault and conductance deviation. In this study, a compact leaky integrate-and-fire neuron circuit has been designed, with resilience to synaptic device state variations, for hardware implementation of spiking neural networks (SNNs). The proposed neuron circuit is simulated on the 0.35-mu m Si complementary metal-oxide-semiconductor technology node by a series of circuit simulations based on HSPICE. The proposed circuit occupies a reduced area and exhibits low power consumption (14.7 mu W per spike). Furthermore, the optimized circuit design results in a high degree of tolerance toward input-current variations arising from conductance-state variations in the synapse array. Hence, the proposed neuron circuit would be capable of substantially improving the area efficiency and reliability in the realization of the hardware-oriented SNN architectures.
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