Organic Ternary Logic Inverter Using Negative Transconductance Pull-Down Switching Transistor

Abstract

This study presents a novel approach to designing a ternary inverter utilizing a negative transconductance (NTC) behavior field-effect transistor (FET) with pull-down switching. The NTC FET is constructed by combining partially-deposited p-type and n-type semiconductors. The key advantages of the NTC FET, including hysteresis-free operation and a clear peak-to-valley current ratio (PVCR) of 9.6 A/A, enable the proposed ternary inverter to exhibit stable transient characteristics over a duration of 250 sec, covering three logic states. The effectiveness of the design is further supported by experimental results and simulation analysis.