Organic Ternary Logic Inverter Using Negative Transconductance Pull-Down Switching Transistoropen access
- Authors
- Kim, Somi; Jeon, Yunchae; Cho, Hong-Rae; Kim, Chang-Hyun; Yoo, Hocheon
- Issue Date
- Apr-2024
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Multi-valued logic; ternary logic circuit; negative transconductance; organic field effect transistor
- Citation
- IEEE ELECTRON DEVICE LETTERS, v.45, no.4, pp 590 - 592
- Pages
- 3
- Journal Title
- IEEE ELECTRON DEVICE LETTERS
- Volume
- 45
- Number
- 4
- Start Page
- 590
- End Page
- 592
- URI
- https://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/92106
- DOI
- 10.1109/LED.2024.3368346
- ISSN
- 0741-3106
1558-0563
- Abstract
- This study presents a novel approach to designing a ternary inverter utilizing a negative transconductance (NTC) behavior field-effect transistor (FET) with pull-down switching. The NTC FET is constructed by combining partially-deposited p-type and n-type semiconductors. The key advantages of the NTC FET, including hysteresis-free operation and a clear peak-to-valley current ratio (PVCR) of 9.6 A/A, enable the proposed ternary inverter to exhibit stable transient characteristics over a duration of 250 sec, covering three logic states. The effectiveness of the design is further supported by experimental results and simulation analysis.
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