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Analysis of various DRAM devices from power consumption's perspective Go to Link

Jeon, Dong-Ik; Lee, Min-Kyu; Chung, Ki-Seok

ArticleIssue Date2015CitationProceedings of the 2015 IEEE International Conference on Networking, Architecture and Storage, NAS 2015, pp.359 - 360PublisherInstitute of Electrical and Electronics Engineers Inc.

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CasHMC: A Cycle-Accurate Simulator for Hybrid Memory Cube Go to Link

Jeon, Dong-Ik; Chung, Ki-Seok

ArticleIssue Date2017CitationIEEE Computer Architecture Letters, v.16, no.1, pp 10 - 13PublisherInstitute of Electrical and Electronics Engineers

SCIESCOPUSKCI

DRBAC: Dynamic Row Buffer Access Control for Power and Performance of DRAM Systems Go to Link

Jeon, Dong-Ik; Chung, Ki Seok

ArticleIssue Date2018CitationJOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.18, no.3, pp.307 - 314PublisherIEEK PUBLICATION CENTER

SCIESCOPUSKCI

Low Power and High Performance Level-up Shifters for Mobile Devices with Multi-V-DD Go to Link

Jeon, Dong-Ik; Han, Kwang-Soo; Chung, Ki-Seok

ArticleIssue Date2017CitationJOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.17, no.5, pp 577 - 583Publisher대한전자공학회

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Novel level-up shifters for high performance and low power mobile devices Go to Link

Jeon, Dong-Ik; Han, Kwang-Soo; Chung, Ki-Seok

ArticleIssue Date2013CitationDigest of Technical Papers - IEEE International Conference on Consumer Electronics, pp 181 - 182

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Runtime Memory Controller Profiling with Performance Analysis for DRAM Memory Controllers Go to Link

Jeon, Dong-Ik; Lee, Min-Kyu; Kim, Ji-Chan; Chung, Ki Seok

ArticleIssue Date2018CitationJOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, v.27, no.8PublisherWORLD SCIENTIFIC PUBL CO PTE LTD

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Ultra low power and high speed FPGA design with CNFET Go to Link

Han, Kwang-Soo; Jeon, Dong-Ik; Chung, Ki-Seok

ArticleIssue Date2012Citation2012 International Symposium on Communications and Information Technologies, ISCIT 2012, pp.828 - 833PublisherIEEE

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Browsing by Jeon, Dong-IkAuthor

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