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A 108Gb/s PAM-8 CTLE+FFE Receiver Frontend with 1.4Vppd Input Range in 28nmGo to Link

Lee, Sangwan; Jo, Hanhee; Jeong, Heedo; Jung, Hwanseok; Han, Jaeduk

ArticleIssue Date2026Citation2025 IEEE Asian Solid-State Circuits Conference, A-SSCC 2025 - Proceedings, pp 145 - 147PublisherInstitute of Electrical and Electronics Engineers Inc.
SCIESCOPUS
A 36-Gb/s Single-Ended PAM-4 Receiver With Voltage-Feedback DFE in 40-nm CMOS TechnologyGo to Link

Sim, Taeyang; You, Geunyoung; Jung, Hwanseok; Lee, Donghun; Shin, Taeho; Han, Jaeduk

ArticleIssue Date2026CitationIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.73, no.4, pp 2759 - 2770PublisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
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