A 36-Gb/s Single-Ended PAM-4 Receiver With Voltage-Feedback DFE in 40-nm CMOS Technology

Abstract

This paper presents a single-ended four-level pulse amplitude modulation (PAM-4) receiver for memory interfaces. The front-end employs a T-coil, an inverter-based hybrid continuous-time linear equalizer (CTLE), and a decision-feedback equalizer (DFE) to compensate for complex channel losses. Additionally, a cross-coupled pair (XCP) is incorporated to enhance the single-to-differential (S2D) conversion performance of the CTLE, which results in improved differential-mode gain. Unlike conventional current-mode DFE implementations, the proposed DFE employs voltage-feedback using resistive digital-to-analog converters (DACs), source followers (SFs), and voltage multiplexers (VMUXes) to ensure robust operation. To verify the capability of the proposed single-ended PAM-4 receiver, a prototype is fabricated using 40-nm CMOS technology, occupying an active area of 0.039 mm2. The 36 Gb/s single-ended PAM-4 receiver achieves a bit error rate (BER) below 10-12 over a channel exhibiting 11.71 dB insertion loss at 9 GHz. The receiver consumes 51.89 mW, achieving an energy efficiency of 1.44 pJ/bit.