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A 0.5-1 V,-68 dB Power Supply Rejection Capacitorless Analog LDO Using Voltage-to-Time Conversion in 28-nm CMOSGo to Link

Jang, Jun-Hwan; Gwon, Hui-Dong; Kong, Tae-Hwang; Yang, Jun-Hyeok; Choi, Byong-Deok

ArticleIssue Date2022CitationIEEE JOURNAL OF SOLID-STATE CIRCUITS, v.57, no.8, pp 2462 - 2473PublisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
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