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A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology Go to Link

Wang, Zhongkai; Choi, Minsoo; Kwon, Paul; Lee, Kyoungtae; Yin, Bozhi; Liu, Zhaokai; Park, Kwanseo; Biswas, Ayan; Han, Jaeduk; Du, Sijun, et al.

ArticleIssue Date2022CitationDigest of Technical Papers - Symposium on VLSI Technology, v.2022-June, pp 34 - 35

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A 24.6-29.6GHz Hybrid Sub-Sampling PLL with Tri-State Integral Path Achieving 44fs Jitter and -254.8dB FOM in 28nm CMOS Go to Link

Wang, Zhongkai; Choi, Minsoo; Kwon, Paul; Liu, Zhaokai; Yin, Bozhi; Lee, Kyoungtae; Park, Kwanseo; Biswas, Ayan; Han, Jaeduk; Du, Sijun, et al.

ArticleIssue Date2024CitationProceedings - IEEE International Symposium on Circuits and Systems, pp 1 - 5PublisherIEEE

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A Ring-Oscillator Sub-Sampling PLL With Hybrid Loop Using Generator-Based Design Flow Go to Link

Wang, Zhongkai; Choi, Minsoo; Wright, John; Lee, Kyoungtae; Liu, Zhaokai; Yin, Bozhi; Han, Jaeduk; Du, Sijun; Alon, Elad

ArticleIssue Date2022CitationProceedings - IEEE International Symposium on Circuits and Systems, v.2022-May, pp.2881 - 2885PublisherInstitute of Electrical and Electronics Engineers Inc.

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Browsing by Yin, BozhiAuthor

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