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A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology
- Authors
- Wang, Zhongkai; Choi, Minsoo; Kwon, Paul; Lee, Kyoungtae; Yin, Bozhi; Liu, Zhaokai; Park, Kwanseo; Biswas, Ayan; Han, Jaeduk; Du, Sijun; Alon, Elad
- Issue Date
- Jun-2022
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Keywords
- 28nm; CMOS; SerDes; Sub-sampling PLL; Transmitter
- Citation
- Digest of Technical Papers - Symposium on VLSI Technology, v.2022-June, pp.34 - 35
- Indexed
- SCOPUS
- Volume
- 2022-June
- Start Page
- 34
- End Page
- 35
- ISSN
- 0743-1562
- Abstract
- This paper presents a complete 200Gb/s PAM-4 transmitter (TX) in 28nm CMOS technology. The transmitter features a hybrid sub-sampling PLL (SSPLL) with a delta-sigma (?S) modulator, clock distribution network with flexible timing control, and data path with a hybrid 5-tap Feed-Forward Equalizer (FFE) and T-coil for bandwidth extension. The prototype chip achieves 4.69 pJ/bit efficiency, 54mV eye height, 0.27UI eye width, and 97% RLM under -6dB channel loss at 50GHz.
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Related Researcher
- Han, Jaeduk
- COLLEGE OF ENGINEERING (SCHOOL OF ELECTRONIC ENGINEERING)